In personal computers and other information processing terminals, a CPU which controls processing in the information processing terminal, a memory in which are stored programs to control the CPU and various data related to control, and other peripheral device which is a network interface card (NIC) and so on, are connected by a signal line (bus). The CPU stores data stored in the peripheral device in the memory, and by accessing the data stored in memory and sending the result of the processing back to the peripheral device, data is transferred between the peripheral device and memory.
FIG. 1 is a block diagram of the configuration of the information processing terminal, used to explain conventional data transfer. In FIG. 1, the CPU 3, which controls processing in the information processing terminal 1, and the memory 4 storing programs to control the CPU 3 and various data relating to control, are connected by a system bus 6 which is faster than a common bus 7. A chipset 5 serves to adjust bus speed differences, via data transfer over the common bus 7 and system bus 6. In this specification, the CPU 3, memory 4, and chipset 5 connected by the system bus 6 are together called a host 2.
The peripheral device (NIC) 9 is one example of the peripheral device connected to the host 2 via the common bus 7, and connects the information processing terminal 1 to a network 10. The common bus 7 can also be connected to other peripheral device 8, such as for example a graphics card, hard disk drive, floppy disk, CD (Compact Disc), DVD (Digital Versatile Disk), MO (Magneto-Optical disc), and various other drives and similar using replaceable media.
In the configuration of FIG. 1, when the NIC 9 receives data from the network 10, the NIC 9 transfers the data to the memory 4 of the host 2, and stores the position (storage address) at which the received data is stored (in the host memory 4). When data transfer is completed, an interrupt request is issued, and an interrupt is sent to the CPU 3. This interrupt processing, which is executed upon completion of transfer to the host memory 4 of data received from the network 10 by the NIC 9, is called an external reception interrupt.
The CPU 3 receives the interrupt request, halts normal processing, and executes the external reception interrupt processing. Here, (1) the CPU 3 confirms the storage address for the received data with the NIC 9, accesses the storage address, and performs processing of the received data. Then, (2) after completion of processing of the received data, the CPU 3 determines from the NIC 9 whether, during the processing of (1), the NIC 9 has further transferred data received from the network to the host memory 4.
If further data transfer is confirmed, the CPU 3 repeats the processing of (1) and (2). Thus in the prior art, when new data is received from the network 10 by the NIC 9 during external reception interrupt processing in processing to transfer data received from the network 10 to the host memory 4, the common bus 7 is used a plurality of times in order for the CPU 3 to perform processing to determine whether data has been received by the NIC 9. Consequently the common bus 7 usage rate for other peripheral device 8 connected to the common bus 7, enabling use in data transfer, is lowered, and there is the problem that the performance of the information processing terminal 1 is degraded.
Further, there is a similar problem when transferring data to be transmitted to the network 10 from the host memory 4 to peripheral device (the NIC) 9. When the NIC 9 transmits a plurality of data sets to the network 10, the NIC 9 stores, in memory provided in the NIC 9 not shown, the original storage address (in the host memory 4) in which the transmission data is stored. When the NIC 9 completes transmission to the network 10 of the first data set, an interrupt is issued, and an interrupt is sent to the CPU 3. The interrupt processing executed when the NIC 9 completes data transmission to the network 10 is called an external transmission interrupt.
Upon receiving the interrupt request, the CPU 3 halts normal processing and performs external transmission interrupt processing. Then, (3) the CPU 3 confirms the storage address of transmission data with the NIC 9, and performs necessary processing. Necessary processing may be, for example, processing to release memory 4 specified by the storage address. Then, (4) after completion of necessary processing, the CPU 3 determines from the NIC 9 whether, during the processing of (3), the NIC 9 has further completed transmission of other data received to the network 10.
If completion of further data transmission is confirmed, the CPU 3 repeats the processing of (3) and (4). Hence in the data transfer processing of the prior art, similarly to cases in which data is received from the network 10, when data is transmitted to the network 10 also, the usage ratio of the common bus 7 which can be used by other peripheral device 8 connected to the common bus 7 for data transfer is lowered, and so there is the problem that performance of the information processing terminal 1 is degraded.
As advanced technology relating to interrupt processing during data transfer, a method has been disclosed of writing to a storage area packets received from the network by a DMA portion provided in the network interface, without passing through the CPU of the host device (Japanese Patent Laid-open No. 2003-87255). However, in Japanese Patent Laid-open No. 2003-87255, there is no mention of alleviation of the degradation in performance due to accessing of the communication interface portion by the CPU via the common bus a plurality of times during interrupt processing after the completion of writing to the storage area.
Further, an infrared ray data transmission method has been disclosed in which, by setting the number of transmission packets in advance, the issuing of interrupts is suppressed until the pre-set number of packets has been transmitted (Japanese Patent Laid-open No. 11-103330). However, in Japanese Patent Laid-open No. 11-103330, there is no mention of alleviation of the degradation in performance due to accessing of peripheral device by the CPU via the common bus a plurality of times in interrupt processing after the end of transfer to memory.